Using state-of-the-art EDA design tools, Acronics’ engineers can take the design specification, select appropriate components and develop the corresponding schematics. A bill of materials is provided early in the design cycle so that component ordering can take place.With in-house developed tools, we can connect large pin-count elements like FPGA/ASIC devices quickly and accurately. Symbol/Geometry generation is also provided if required. Using in-house tools, our engineers have the capability to generate these directly from datasheets, thus greatly minimizing the probability for entry errors.
Interconnections between devices such as dense BGA and RAM devices at high speeds and edge rates are no longer a trivial connectivity issue. In addition to this, running these high speed signals through connectors can be a daunting task without the introduction of signal degradation and crosstalk.Acronics employs best practice techniques for the simulation of high-speed transmission lines incorporating I/O, PCB and connector models to the required degree of accuracy. This in turn leads to the use of appropriate layout, termination, and tracking methods to guarantee success on first power up. Signal Integrity Analysis can also be performed where less than ideal layout and tracking is warranted, to evaluate the performance of signals under these conditions.